Here's what was posted to Facebook on 15th of oct by JohnW. (Should someone be curious, no photos though)
Lakewest Audio
Admin
A well overdue progress updater (I apologize for my absence since I've been so focused on the development).
I promised noise floor performance plots of the Array regulator – whose performance is pretty close to the noise floor limitations of the analyzer system (Plots below of analyzers noise floor (50Hz component at ~ -150dB) & the Array regulators output).
I've been dividing my time between FPGA Firmware development and working on the Clock circuit – both are progressing well.
I've built and am developing / testing the x32 - 16bit “Multibit” DAC array (with discrete Array PSU, but for this FPGA firmware development PCB spin - an Opamp based output stage (to ease development testing) the production boards will have a discrete output stage). The 40W ribbon cable goes to the FPGA Dev board.
I've attached photos of the array development PCB, with the underside showing the larger number of Array PSU decoupling capacitors.
As the main design progress, I've made the decision to keep the Clock block and digital input cards (And possibly the output stages) common between the Multi-bit Dac array and Low-Bit DAC array designs – this allows customer upgrades and reduces the development time moving forward, with the Multibut DAC array the first version to ship.
In essence, I believe the Multibit DAC array will sound better – but the Low Bit DAC array will measure better... listening tests to confirm.
I'm still coding the firmware for the Multibit array – I'm constantly battling FPGA resource / clock speed issues, as there are 32x 16bit DAC's in the array – and having to address each individually (each with 35bits wide modulator data paths x32 modulators etc) rapidly eats into the FPGA resources – So I'm having to conceive “clever” ways to reduce the resources without compromising digital performance (without having to reduce data bitdepths etc).
The clock section... the heart the design... still progressing (painfully) – in the past couple of weeks I've made some major leaps in direction and waiting on chips to arrive to confirm the idea.
Lakewest Audio
Admin
A well overdue progress updater (I apologize for my absence since I've been so focused on the development).
I promised noise floor performance plots of the Array regulator – whose performance is pretty close to the noise floor limitations of the analyzer system (Plots below of analyzers noise floor (50Hz component at ~ -150dB) & the Array regulators output).
I've been dividing my time between FPGA Firmware development and working on the Clock circuit – both are progressing well.
I've built and am developing / testing the x32 - 16bit “Multibit” DAC array (with discrete Array PSU, but for this FPGA firmware development PCB spin - an Opamp based output stage (to ease development testing) the production boards will have a discrete output stage). The 40W ribbon cable goes to the FPGA Dev board.
I've attached photos of the array development PCB, with the underside showing the larger number of Array PSU decoupling capacitors.
As the main design progress, I've made the decision to keep the Clock block and digital input cards (And possibly the output stages) common between the Multi-bit Dac array and Low-Bit DAC array designs – this allows customer upgrades and reduces the development time moving forward, with the Multibut DAC array the first version to ship.
In essence, I believe the Multibit DAC array will sound better – but the Low Bit DAC array will measure better... listening tests to confirm.
I'm still coding the firmware for the Multibit array – I'm constantly battling FPGA resource / clock speed issues, as there are 32x 16bit DAC's in the array – and having to address each individually (each with 35bits wide modulator data paths x32 modulators etc) rapidly eats into the FPGA resources – So I'm having to conceive “clever” ways to reduce the resources without compromising digital performance (without having to reduce data bitdepths etc).
The clock section... the heart the design... still progressing (painfully) – in the past couple of weeks I've made some major leaps in direction and waiting on chips to arrive to confirm the idea.