What would be the ideal spec for L1
It's not too critical but in an engineering sense it needs to do the following things: -
1. It needs to provide sufficient increase in impedance as frequency rises, to prevent the decoupling cap on the clock module from reducing phase margin in the AD797 regulator section.
2. It needs to provide some loss (i.e. low-ish Q) to prevent the LC combination of the choke and the clock decoupling capacitor forming a resonant circuit. This can be acheived by using suitable ferrites (which appear elecrically as if a resistor is placed across the choke, to damp it) or using a high-Q choke and damping it with a resistor. If the clock module comes with a choke, I'd trust Guido to have done his homework!
3. It ideally should provide an even impedance looking back from the clock to the regulator section - the AD797's output impedance will rise as the open loop gain falls off and the local decoupling at the clock output becomes ineffective w.r.t. the clock, so the local bypass 'takes over' and results in a steady reduction in supply impedance, up to the point the clock decoupling becomes reactive.
I think that just about covers it
In reality, it's easier to determine by experimentation and isn't likely to be so critical in a digital application, providing things are well behaved and stable, which is easiest to see by probing with a 'scope (which I'll do once we have some boards).
I need an excuse to play with my new toy (gratuitous geek pic attached)...
Andy.