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MDAC First Listen (Part 00101010)

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JohnW said:
The modulator is operated from the clean 84MHz clock located besides the DAC, the fractional derived clock is only for inputting the data but plays no direct part in the actual conversion - its what makes the ESS design so special. This only holds true when the DPLL values are fixed, otherwise you face concerns about the use of ASRC with non synchronous data (changing DPLL values) - we don't need to reject jitter due to the synchronous clock structure in ASync USB mode.

The ESS ASRC is not your typical ASRC, but its still best to avoid - it just feels "cleaner" more direct if nothing else...
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Is this how it will work for the non-asrc S/PDIF mode too?
 
John
I think you have previously indicated that the miniDSP active crossover functionality will not be immediately available on the FDAC and that it will need a subsequent firmware update - have I got that right? I know you will probably hate this question but if that is correct, can you give me a realistic estimate of how long after release of the FDAC is it likely to be before that update comes along?
 
JohnW said:
The modulator is operated from the clean 84MHz clock located besides the DAC, the fractional derived clock is only for inputting the data but plays no direct part in the actual conversion - its what makes the ESS design so special. .....
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Having just seen this again, it does bring up another question for me - is there not fractional division happening in the conversion inside the ESS DAC chip then? If the data is modulated @84MHz, the output needs to be demodulated to it's correct output sample rate 44.1Khz or 48Khz (or whatever it may be) - this involves a non-integer operation inside the ESS DAC chip, no?
 
jkeny said:
Having just seen this again, it does bring up another question for me - is there not fractional division happening in the conversion inside the ESS DAC chip then? If the data is modulated @84MHz, the output needs to be demodulated to it's correct output sample rate 44.1Khz or 48Khz (or whatever it may be) - this involves a non-integer operation inside the ESS DAC chip, no?
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why would it? you don't reconvert to pcm after the delta-sigma modulator do you? It's a dac.
 
iansr said:
John
I think you have previously indicated that the miniDSP active crossover functionality will not be immediately available on the FDAC and that it will need a subsequent firmware update - have I got that right? I know you will probably hate this question but if that is correct, can you give me a realistic estimate of how long after release of the FDAC is it likely to be before that update comes along?
Click to expand...

Best avoid holding your breath on when the MiniDSP software will be released for the FDAC as our priority is to release the FAC's into production - also I cannot speak for miniDSP's internal timelines...

The firmware update is simply download via the internet as per the MDAC updates... but I don't see it happening until atleast the middle of next year...
 
tunkejazz said:
BTW, will the new chassis have a subwoofer out? :)
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With the DSP we can have subwoofer output via SPDIF - but no "Pre-processed" Analogue subwoofer output as the FDAC is only a "2 channel" DAC (unless you add the slave units).
 
John, does the FDAC's DSP capability extend to RIAA equalisation curves, etc., and if so, does that spell the end for the Lakewest phono stage project?
 
adamdea said:
Is this how it will work for the non-asrc S/PDIF mode too?
Click to expand...

For non synchronous SPDIF inputs the MDAC relies on the ASRC mode of the ESS for Jitter attenuation, although its de-jittered via x2 stages of Jitter attenuation by the cascaded WM8806's.

FDAC will initially use the ESS ASRC, but later we can use a short memory buffer + DPLL so bypassing the ASRC.
 
JTC said:
John, does the FDAC's DSP capability extend to RIAA equalisation curves, etc., and if so, does that spell the end for the Lakewest phono stage project?
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No, the Phono stage will offer selectable flat or RIAA EQ modes so you can choose between Analogue or digital EQ. (Pure DSD requires Analogue EQ).
 
JohnW said:
Best avoid holding your breath on when the MiniDSP software will be released for the FDAC as our priority is to release the FAC's into production - also I cannot speak for miniDSP's internal timelines...

The firmware update is simply download via the internet as per the MDAC updates... but I don't see it happening until atleast the middle of next year...
Click to expand...

Thanks John, tells Me what I need to know. I will probably look at an interim solution in the meantime, either 4x10HD or the Hypex DLCP.
 
JohnW said:
For non synchronous SPDIF inputs the MDAC relies on the ASRC mode of the ESS for Jitter attenuation, although its de-jittered via x2 stages of Jitter attenuation by the cascaded WM8806's.

FDAC will initially use the ESS ASRC, but later we can use a short memory buffer + DPLL so bypassing the ASRC.
Click to expand...
Thanks- is that not going to be on the F-dac from the outset? Presumably the memory buffer will be built in won't it.
I have to confess I'm quite attached to using toslink
 
adamdea said:
Thanks- is that not going to be on the F-dac from the outset?
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No sadly the initial release software will be a basic "get you going" software and overtime we will build up the more advanced features.

The Digital controlled VCXO / Short memory buffer involves a lot of advance control loop theory, well above my expertise - and I'm sure Dominiks not looking forward to getting it all going...

adamdea said:
Presumably the memory buffer will be built in won't it. I have to confess I'm quite attached to using toslink
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Yes, the FDAC will have the required hardware from day 1 - we just need to "enable" the features via the software updates as and when we have completed there development.
 
Are the slaves a day one feature?
I guess the ability to use them for AV surround channels is relying on Dominik being able to mod an Oppo (or other). Until that's done , the slaves and additional 8200mbs are a bit redundant for me.
 
JohnW said:
No sadly the initial release software will be a basic "get you going" software and overtime we will build up the more advanced features.
Click to expand...
Oh well with cascaded 8804 (I think you said 8806's, but I can't find them) I assume that the jitter will be pretty well attenuated above 100hz, so the DPLL won't have to be too busy.
 
adamdea said:
Oh well with cascaded 8804 (I think you said 8806's, but I can't find them) I assume that the jitter will be pretty well attenuated above 100hz, so the DPLL won't have to be too busy.
Click to expand...

Sorry, Yes I meant the WM8804 / WM8805...
 
PhilCTTE said:
Are the slaves a day one feature?
I guess the ability to use them for AV surround channels is relying on Dominik being able to mod an Oppo (or other). Until that's done , the slaves and additional 8200mbs are a bit redundant for me.
Click to expand...

The Slaves support will be enabled with the phase 2 software build.

Phase 0 is an internal "test all PCB functions" software.

Phase 1 is the first "basic get you going release"

Phase 2 released about 6 months later where we expand the feature set / Slave interfaces & DSP etc.

The advanced features will be incrementally added so there will be no single "big" leap to phase 2...
 
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