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MDAC First Listen (Part 00101010)

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Non on the design of the digital PCB as priority is the FDAC analogue PCB and chassis.

What will happen is that the Analogue PCB and chassis will goto production first, and the digital PCB will be fitted once they have been built up.

I can design a very simple Digital PCB to allow testing of the analogue board - I can see the 200 odd FDAC's sitting in the factory waiting for the digital board to be fitted so they can be finally shipped.

The Digital PCB requires little testing, basically it works or it does not so while its the last to be developed, its low risk.

Am I correct in which component/function goes where below?

Digital board: Various digital inputs/receivers eg USB, S/PDIF ...

Analog board: DAC's, Clocks, ADC, FPGA, Analog out
 
Am I correct in which component/function goes where below?

Digital board: Various digital inputs/receivers eg USB, S/PDIF ...

Analog board: DAC's, Clocks, ADC, FPGA, Analog out

The FPGA's are on the digital PCB, but otherwise correct - the digital board is "Simple" but will take about 2 months... We can be building and testing the FDAC in the meantime - and fit the digital PCB at the last stage.
 
Thats a real big question - without the Clocklocking, the Detox's prime purpose is to "equalize" the quality of the USB data stream. However your "USB Card" which is hung of the optical PCIexprsss isolation link should do a very good job, certainly magnitudes better then your typical PC USB port. But whos to say how good really the USB output is - I still suspect the Detox's output will be significantly cleaner :)

As you already have a good "USB port" and cannot clock-lock the Detox to your DAC you will benefit less then others from the Detox... but lets see (hear) :)



No none, its a very clean supply rail so no harm can be done.

Understood. Thanks.
 
John, given there is now space on the FDAC, for the balanced headphone out, would you use the (somewhat industry standard) 4-way female XLR balanced connection: 1 left positive, 2 left negative, 3 right positive, 4 right negative

Give me a week or so to answer as I'll be working on the connector arrangement so the vendor can produce the completed ID drawings and start on the chassis prototypes.
 
One day Dominik swapped the naming of the filters behind my back without telling me - and I was so So very upset and confused with myself because all of a sudden I preferred the other filter. After about half a day!!!! he just smiled and said he was just testing me - so that's a double blind test if there ever was one! :)

My expertise lies elsewhere. I was once handed a G&T by an air stewardess and upon tasting it promptly identified it as Tankerey. :cool:
 
John, do you still have slots for the modified 8200MB? Given that I have finally decided to go all in for the FDAC, I will have to sell my current Naim system (for good!) :)

Will you finally install the tube?
 
Yes, we use a PLL to derive the audio clock from the 84MHz master clock in the MDAC - the Detox is then locked to the 84MHz master clock 84MHz/7). The Modulator is operated from the 84MHz - everything is synchronous so that the DPLL has a fixed coefficient without modulation.
Sorry for the follow-up question but are you saying that your audio clocks 22.5796MHz & 24.576MHz (fed to your DAC) are derived by fractional division of the 84MHz master clock?
 
Sorry for the follow-up question but are you saying that your audio clocks 22.5796MHz & 24.576MHz (fed to your DAC) are derived by fractional division of the 84MHz master clock?

The MDAC's ASync USB mode the audio rate clocks are derived by fractional division of the 84MHz master clock, but its not 512fs related (I guess your thinking typical XMOS based designs) - FDAC has a very different clocking structure but again everything by design is fully synchronous.

With the ESS the modulator can operate at any rate it does not need to be audio related - whats important is to insure that the DPLL operates with a fixed number without modulation over time.

With non synchronous data the DPLL would be constantly changing which results in unwanted modulation and related artifacts. With the Synchronous clock structure used in the MDAC, the DPLL values are fixed. The input data verses modulator rate is locked / fixed.

Its important to understand that a modulator can operate at any rate independent of the audio data, the fact that a typical DAC operates the modulator at an audio related rate is just due to the local clocks available.
 
John, do you still have slots for the modified 8200MB? Given that I have finally decided to go all in for the FDAC, I will have to sell my current Naim system (for good!) :)

Will you finally install the tube?

I have a couple of pallets of the amps so plenty to go around!

If the modifications where only to remove the design defects and convert to fully balanced operation then it would be a relativity easy job - but as we all know I tend to make my life difficult and push the boundary's, so adding the tube requires an extra 6V heater supply = small transformer + PCB, which complicates the picture.

I guess in my heart I know I have to add the tube but don't see when I will have the time - that said I need to convert these units back into cash so I can pay for the new custom VFET chassis - so I will need to work on these amps this side of Christmas!!!

Now that I have my small lab - I really need to find someone who could work with me to help ease my workload.... anyone want a job in the Czech Rep? :)

When I first started out in HiFi I would have loved such a job opportunity - not to mention living in a country surrounded by beautiful ladies and cheap beer! :p
 
Is there not someone on an electronics/engineering course at Renata's university, who would want some real life experience ?

They don't have an Electronics Dept at Renata's university,... only in Prague and Brno :( Yes I need a second "Dominik" here in Czech.
 
The MDAC's ASync USB mode the audio rate clocks are derived by fractional division of the 84MHz master clock, but its not 512fs related (I guess your thinking typical XMOS based designs) - FDAC has a very different clocking structure but again everything by design is fully synchronous.

With the ESS the modulator can operate at any rate it does not need to be audio related - whats important is to insure that the DPLL operates with a fixed number without modulation over time.

With non synchronous data the DPLL would be constantly changing which results in unwanted modulation and related artifacts. With the Synchronous clock structure used in the MDAC, the DPLL values are fixed. The input data verses modulator rate is locked / fixed.

Its important to understand that a modulator can operate at any rate independent of the audio data, the fact that a typical DAC operates the modulator at an audio related rate is just due to the local clocks available.

Thanks for that explanation - I have to think about it some more but an immediate issue pops into my head - doesn't a local hardware clock (situated as close to the DAC as possible) usually represent the lowest jitter option available?
Are you saying that a fractional division of a clock is a better option when it can be fed upstream & used to synchronise all processes which require clocking?
In other words multiple clock domains derived from low jitter local clocks is audibly worse than synchronised clocks derived by fractional division ( a known source of jitter) from a single master clock?
 
The modulator is operated from the clean 84MHz clock located besides the DAC, the fractional derived clock is only for inputting the data but plays no direct part in the actual conversion - its what makes the ESS design so special. This only holds true when the DPLL values are fixed, otherwise you face concerns about the use of ASRC with non synchronous data (changing DPLL values) - we don't need to reject jitter due to the synchronous clock structure in ASync USB mode.

The ESS ASRC is not your typical ASRC, but its still best to avoid - it just feels "cleaner" more direct if nothing else...
 
The modulator is operated from the clean 84MHz clock located besides the DAC, the fractional derived clock is only for inputting the data but plays no direct part in the actual conversion - its what makes the ESS design so special. This only holds true when the DPLL values are fixed, otherwise you face concerns about the use of ASRC with non synchronous data (changing DPLL values) - we don't need to reject jitter due to the synchronous clock structure in ASync USB mode.

The ESS ASRC is not your typical ASRC, but its still best to avoid - it just feels "cleaner" if nothing else...

Ah, right, the penny has dropped - thanks!
I had always assumed that synchronous meant the same clock signal was used at the ESS DAC & upstream - I hadn't envisaged a fixed rate derived clock being used upstream.

Agreed with ESS asynch Vs synch clocking - it sounds better synched but from what you say it's the drifting of DPLL that causes these audible issues, not the DPLL itself?
 
Hi John

Just a thought, but most of us are based in the UK?

I have no idea if he would lend himself to this opportunity, or if it suited you either but Kevin is very talented at this kind of thing. He has a very good reputation repairing AUDIOLAB and TAGMcLaren amplifiers and Processors, at very reasonable fees all considered.

He is a genuine guy; I'm sure there are ex TMA people on here that could/would attest.

Anyway just an idea, if it made sense and parties are willing.

Ps. I have no financial affiliation here whatsoever. Also his other passion is the Nurburghring and races there often enough...not sure how far your place and this exactly are apart, if collection were feasible.

I have a couple of pallets of the amps so plenty to go around!

If the modifications where only to remove the design defects and convert to fully balanced operation then it would be a relativity easy job - but as we all know I tend to make my life difficult and push the boundary's, so adding the tube requires an extra 6V heater supply = small transformer + PCB, which complicates the picture.

I guess in my heart I know I have to add the tube but don't see when I will have the time - that said I need to convert these units back into cash so I can pay for the new custom VFET chassis - so I will need to work on these amps this side of Christmas!!!

Now that I have my small lab - I really need to find someone who could work with me to help ease my workload.... anyone want a job in the Czech Rep? :)

When I first started out in HiFi I would have loved such a job opportunity - not to mention living in a country surrounded by beautiful ladies and cheap beer! :p
 
FYI...Someone from AVForums just informed me he is away for 2 weeks, not sure if he will be checking emails though...
 
Also his other passion is the Nurburghring and races there often enough...not sure how far your place and this exactly are apart, if collection were feasible.[/QUOTE]

Looking on a map Nürburgring looks closer to London than to Brno...
 
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