John Phillips
pfm Member
FYI, there was a rather entertaining presentation from ESS (SABRE DACs) at a RMAF which shows complex/chaotic state variable behaviour and noise levels depending on signal input in one-bit sigma-delta modulators. It reveals that ESS has patented secret sauce to minimize the audible impact (sorry that this version of the online video may not work in your IT but the slide deck is available from ESS)....SACD tries to avoid this as much as possible by measures like keeping the peak signal levels encoded well below the max range nominally possible. But you can't beat the maths...
I remember reading the Lipschitz paper you mentioned earlier and deciding (maybe based on not enough understanding) that the right cure was a multi-bit SDM at the core of a DAC with enough margin by design to avoid overload problems. However I never got round to trying out that hypothesis.