Andrew L Weekes
Reverse Engineer
To help you visualise the effect of jitter, the attached image may help*.
Ignore the maths element, just look at the diagram at the right hand side of the picture.
As small portion of a signal being sampled is represented by the 'S' shaped curve. The clock being used to sample the signal is represented by the image around the 'encode' label.
This clock should ideally be a single edge, but is represented here by the jittery signal, with a time variation (jitter) represented by dt.
Since this clock is jittery, the position at which it samples the analogue signal changes from sample to sample, this gives rise to a range of output voltages, represented by the error voltage, dV.
You can quite readily see that as frequency rises (i.e. the rise time of the signal rises and the gradient becomes greater) the range of error voltages available for a given clock jitter increase considerably.
Were the clock perfect, one could draw a straight line from between the two points and get a single consistent output voltage every sample.
So you can see that jitter adds actual analogue errors to the input or output signals of an ADC / DAC, which means the reconstructed signal isn't as it should be, but this only happens at the point of conversion between domains.
Andy.
*Image from Analog Devices Net Seminar Using Low Jitter Clocks to Enhance Converter Performance (bottom of page).
Ignore the maths element, just look at the diagram at the right hand side of the picture.
As small portion of a signal being sampled is represented by the 'S' shaped curve. The clock being used to sample the signal is represented by the image around the 'encode' label.
This clock should ideally be a single edge, but is represented here by the jittery signal, with a time variation (jitter) represented by dt.
Since this clock is jittery, the position at which it samples the analogue signal changes from sample to sample, this gives rise to a range of output voltages, represented by the error voltage, dV.
You can quite readily see that as frequency rises (i.e. the rise time of the signal rises and the gradient becomes greater) the range of error voltages available for a given clock jitter increase considerably.
Were the clock perfect, one could draw a straight line from between the two points and get a single consistent output voltage every sample.
So you can see that jitter adds actual analogue errors to the input or output signals of an ADC / DAC, which means the reconstructed signal isn't as it should be, but this only happens at the point of conversion between domains.
Andy.
*Image from Analog Devices Net Seminar Using Low Jitter Clocks to Enhance Converter Performance (bottom of page).