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DIY Jfet phono buffer.

a.palfreyman

a.palfreyman

pfm Member
Bored as I'm using holiday up before year end and poor weather, I've been doing some reading/thinking. (Dangerous, I know...)
Anyway, it seems we haven't had a DIY project for some time, so inspired by threads regarding phono input gain stages suffering Miller capacitance which is essentially too much for MM carts requiring 100-200pF loading, I've put an idea together for a Jfet input buffer. I decided it must use a 'wall wart' for simplicity, using a matched pair of n channel Jfets for DC/temperature stability:
IMG-20231212-150407-292-2.jpg

Essentially it uses a 20-24vdc supply to provide a regulated output of abt 15v. This drives an opamp voltage divider in order to provide a virtual earth between cleaned +/-6.5v supply rails, top of image.
This then feeds the self-biasing Jfet pair (of essentially constant current load) to provide the input buffer with minimal voltage offsets once trimmed. In front of that is a bank of switched resistors/caps to provide variable input loading from 100k down to 36k and capacitive loading of input cable plus 22pF to plus 410pf in reasonable steps.
I decided to put input cap in between loading network and Jfet stage to stop 'switch thumps' when adjusting capacitive loading but not certain this will be necessary when you have essentially 500 to 1000 ohm cart windings connected.

Will it work? Can it be improved on paper prior to build? So, any thoughts?
 
Meant to say I have a pack of 10 J112 to play with. My cheap Chinese meter says they vary from 2.8mA at Vg of 2.0V to 3.5mA at Vg of 2.5V.
This would require a set resistor (Rs1 / Rs2) to be about 700 ohm. I suspect that I'll need a Vgs of (root 3 i.e. mA) x 2.2 or 3.8V for 1mA current so somewhere in the 3k3 to 3k9 value might be about right. We'll see though as that is just a best guess.
Edit. Not so. 2k4 gives me 1.03mA in one of a possible pair. To match this current with the other requires 2k43 +/- few ohms. Reckon 3k3 with 10k VR would fine-tune it.
 
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Yes and a dip stick to build it...
(Me that is ;) )
I used my component holder of my tester with
D to +6.5V, 2k4 S to G and G to OV on clip leads.
IMG-20231212-180017-470-2.jpg

Works a treat.
I have 2 well match pairs, a set of 3 and 3 oddments.
 
If you want to buy good NE5534s - stock-up now; they've just gone out of production! : o

Nice idea by the way - never fiddled with phono, so have no useful input there.

I like the PSU approach - but NB, the way the psu approach is drawn, there is 620 ohms in series with the +ve supply output ?! You could set up a 12-14v supply, and use the opamp to split that / provide a midrail for '0v' (via two resistors, decoupling cap midpoint to 0v and teh NE5534 as a non-inverting unity-gain buffer)
 
Yes the 620R into 100uF is to kill the white noise from the reg. The Jfet circuit is essentially constant bias current, with I believe only a very tiny modulation for ac currents. About 5mV output or so driving the 47k//500pF load. Probably < 1uA.
But I could be plain wrong of course...
Edit:
Anyway @martin clark you made me think. :)
Keep the 620R and 100uF, chuck an npn in there and make a cap multiplier and stick the 0.22uF on the ouput. 2 orders of magnitude less impedance and extra 0.7V per rail to play with. What's not to like?
 
@martin clark I bought plenty of JRC5534D a while back when they were going out of production. They're the best sounding 5534 to my ears. If you need any let me know.
 
New PSU layout with capactitance multiplier:
IMG-20231213-112420-053-3.jpg

I've dropped the standing current in the LM317 a bit (as the 'LZ' variant doesn't need to pass as much current as its big brother) to lower dissipation a bit.
The 6k8 on the NE5534 output is to keep it conducting as the earth currents from the buffer comprise only AC return currents from load and will be TINY....
Any comments/possible improvements?
Andy P
 
Why not just make a gain stage, rather than a buffer - otherwise you will get two lots of noise? To avoid miller capacitance in gain stages, the well known technique is to use a cascode. With bipolars, the capacitance is low enough that you don't need to bother, but as J112 has 28pF between drain and gate. If you ran stage gain of say 10, that would be enough to matter, so some sort of cascode is a good idea. You end up designing a full blown phono stage if you follow this logic to its conclusion!

My other concern would be the noise impact of this stage - I would want to think about the noise contribution of the various source resistors. Once noise is added, it can't be removed.
 
Hi @PigletsDad,
It was just an idea as a buffer to put in front of a phono stage to isolate the MM cart from the capacitance of say a tube phono that has gain (Miller capacitance) on the input which stops you using such as AT carts that want 100 to 200pf.
Yes it would need to be very quiet (2uV?) to keep it >60dB below say typical 3mV cartridge.
Horowitz and Hill indicates the Jfet pair drawn above is typical of oscilloscope inputs and is simple. Also wanted single supply for simplicity, but I'm all ears....
 
Designing a low-noise power supply can be hit and miss as the theory doesn’t necessarily equate with the end result. I use an ADC with a mic input to measure PSU noise, so you can get an FFT analysis, then tweak the circuit for lowest noise.
 
Stealing shamelessly from Flea/ALWSR:
IMG-20231213-150128-166-3.jpg

Sub-section of above circuit, post 9. Voltage ref of 4x LEDs for 7.2V nominal, further filtered with 470R and 47uF to non-inverting input. 'Current sink' on output with bypass cap across 6k8, again to reduce noise.
Can't SIM and don't have your facilities @Avon
but there you go...
2k4 source resistor on Jfet has Johnson noise of 0.9uV @20kHz, so that's most of my 'noise budget' used already...
 
I don' t think rs1 does anything helpful, if you AC couple the output. Rs2 sets the operating current, and generates Johnson noise that modulates the operating current - without a Spice simulation or some algebra I am not sure if that matters, but my guess is that its noise voltage will be added in to the JFET noise voltages. For example, if it were say 1K, so the self bias voltage is a couple of volts ( not sure that is self consistent without looking at transfer function), you would get about 4nV rt/Hz of Johnson noise, which you need to add to JFET noises. You probably need a Spice sim to estimate PSRR, so you can work out a rational target for PSU design. I wouldn't be surprised if you end up adding something like 10nV/rtHz of noise; in 140 rtHz (20K bandwwidth), that is about 2.4uV, using up most of your noise budget, without any contribution from the following stage. Strictly that estimate is wrong, as you need to factor in the cartridge impedance and RIAA curve - but I just wanted to explain that noise is the key design constraint, and everything else has to work round it.

Designing good phono stages is really hard.
 
I don’t think putting a capacitor across the voltage reference diodes will reduce noise, as their impedance is just too low. The filtering after them is good though, but I’d go for a much larger resistor (100k) and use a film cap, which might be quieter than an electrolytic. Start up will be slow, but that shouldn’t matter here?

I could be mistaken on this, but in general, going for unity gain in the op-amp should produce less noise i.e. never amplify a voltage reference.

PS. LEDs in series are noisier than a single Zener diode e.g. BZX55C. Just make sure it sinks enough current.
 
LtSpice is a free download, so anybody can sim if they want (assuming they can find a Windows machine of some sort).
 
Rs1 is there to keep the in-to-out DC across the Jfet to zero so you don't require coupling caps. However, it's probably 'safer' with input and output blocking caps anyway, so yes, Rs1 could be dispensed with if it lowers noise.
Flea uses big R + sml film cap to +input, ALWSR used sml R and big electro, so it's which way which... I took latter route b'cos ne5534 has up 1uA input current.
 
Big R and small C will give more Johnson noise at low frequencies - for example, you wouldn't want to use say 100M and 1nF, even though it gives a 100ms time constant, even if bias current was not a problem.

Again, unless you know the circuit PSRR, you can't make a sensible design choice for the PSU. If PSRR is really good, simple amplified capacitor might be enough.

Film caps don't wear out, don't go noisy and don't need to condition under applied voltage, so there are attractions in using a sanely big film cap, and whatever R it needs. For example, say 10uF and 10K; the bias current will drop maybe 10mV, which doesn't matter.
 
Figure15C_JFETs%20The%20New%20FrontierPart%202.jpg

Figure 15C: Basic JFET source-follower circuits.

If the two JFETs are matched and the two source resistors are equal, then the DC offset will be very small. With two matched K170BLs, I measured less than 1mV offset. (It would probably be even lower if you used here a dual monolithic JFET like the K389BL/V.) DC drifts tend to cancel out as well, because of the matched devices. The circuit also has very low THD.
From here: https://audioxpress.com/article/JFETs-The-New-Frontier-Part-2
Can't readily find info on PSRR tho'.
I suspect (well dodgy!) that as it's a 'modulated current source riding atop a second, matched current source' that PSRR will be reasonable...
 
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