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The John Westlake/Lakewest MDAC/FDAC, VFET and Detox

Clutching at straws springs to mind.

I hope you all manage to get something back. - A most unfortunate situation.
 
From FB (I gave up and made an account)
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Update on the Project progress - PCB design of the DAC array completed and started working on the Analogue output stage.
The first batch of Array IC's I ordered for development arrived today so I've spent today constructing a "rats nested" DAC array and will start coding the FPGA - this will confirm the size of the FPGA required and some basic technical measurements - although performance levels can only be confirmed with a correctly designed PCB - the rats nested array is sub optimal...
I should have first FPGA results by the end of this week.
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At the end he got perfect, everybody was happy. Lets hope this comparison is not too optimistic.
 
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From FB (I gave up and made an account)
--------------------
Update on the Project progress - PCB design of the DAC array completed and started working on the Analogue output stage.
The first batch of Array IC's I ordered for development arrived today so I've spent today constructing a "rats nested" DAC array and will start coding the FPGA - this will confirm the size of the FPGA required and some basic technical measurements - although performance levels can only be confirmed with a correctly designed PCB - the rats nested array is sub optimal...
I should have first FPGA results by the end of this week.
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is that the same rats nest from 2019 where he had to dig out his old phone and charge to get a pic ?
 
On FB today:
I HATE FB!!! I just spent about 30 minutes writing a weekly update and its gone!!! I'm so sorry, but I just dont have the time to repeat it.
A very concise update:-
Written the critical sections of the MDAC2 Array FPGA code - which allowed me to test the concept - works but with some technical performance reservations (with the Rats nest "test" DAC array) - so this week I'll issue a PCB with the DAC Array to allow me to confirm performance - my design target is 120dB Dynamic range - currently, the rats nested array is "only" 106dB...
I've unexpectedly also made significant progress on the FDAC FPGA modulator design last week... So I have a rapid backup solution available... I'm considering designing the DAC boards as selectable options, so the MDAC2 mainboard has the Analogue Stage / PSU - and either MDAC2 or FDAC style DAC arrays can be chosen... a backup plan if I fall significantly short with the MDAC2 array technical performance.
While I was working on the FPGA code, I have no internet access (Email / FB etc). - but I'll be more active now as I work on the PCB.
1730 IC's have arrived - so enough to build the first 55 MDAC2's on the list - more IC's are on order....
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3 years until my retirement. Do you think I’ll have mine before that? Doubt it.
The chase is always better than the catch, https://g.co/kgs/NBcCJC

If this ride ever ends (delivers), I'm going straight around for the next one, its just too much damn fun.

Perhaps others may learn to pay less for their next thrill ride. Too much exposure on vfets I fear, to be comfortable.
 


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