Ciunas Audio
Trade: Ciunas Audio
Really? OK - it's worth looking intoI suspect most PHY's recover the data using a "Clockless" oversampling method like the SPDIF receiver circuits in the ESS DAC's.
Well that might be so but doesn't any jitter on the signal below the PLL corner freq make it through unscathed as well as any current draws used by the PLL in dealing with SI issues? I believe I remember reading that SPDIF PLLs can be listened to as they will produce a signal on their PS which correlates to the data being handled - in other words their current draws were measurably correlated to the data being handledEven if a "tracking" PLL is used there's very little current involved in tracking a signal.
Will do but I have a rough idea of the ESS approach & it's ASRC isn't sonically transparent - it overlays the sound like most ASRCs but somewhat better (edit: which has nothing to do with USB clock recovery - sorry)Search Oversampling data recovery or some such - Dominik uses this method to extract the SPDIF in the FDAC FPGA.
Edit: I have looked into this & a good treatment of what's normally used in USB clock recovery is given in a 2011 Cypress document here
Anyway, it would seem to be something that JS could explain what he meant?